首页> 外国专利> Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component

Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component

机译:具有解耦配置寄存器的硬件将数据流或控制流图划分为时间分隔的子图,并形成并按顺序在组件上实现

摘要

The hardware has a decoupled configuration register and performs programs on a component with a single or multi-dimensional cell structure. Data flow or control flow graphs are partitioned into time-separated sub-graphs and formed sequentially and implemented on the component. An Independent claim is also included for a method for performing programs on a component with a single or multi-dimensional cell structure.
机译:硬件具有解耦的配置寄存器,并在具有一维或多维单元结构的组件上执行程序。数据流或控制流图被划分为时间分隔的子图,并依次形成并在组件上实现。还包括一种独立权利要求,用于在具有一维或多维单元结构的组件上执行程序的方法。

著录项

  • 公开/公告号DE19926538A1

    专利类型

  • 公开/公告日2000-12-14

    原文格式PDF

  • 申请/专利权人 PACT INFORMATIONSTECHNOLOGIE GMBH;

    申请/专利号DE1999126538

  • 发明设计人 VORBACH MARTIN;

    申请日1999-06-10

  • 分类号G06F15/80;G06F9/38;H03K19/173;

  • 国家 DE

  • 入库时间 2022-08-22 01:10:29

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