High frequency - pipeline - decoupling, the presence of ch long design

摘要

A method and apparatus for expediting the processing of a plurality of instructions in a processor is disclosed. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units has a plurality of pipe stages. Further, a decoupling queue is provided to decouple at least one of said pipe stages from another, wherein said decoupling generates non- overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.