Method for the regeneration of a clock signal from a hdb3 - coded input signal and clock regenerator for carrying out the method

摘要

The present invention relates to a method for the regeneration of a clock signal from a hdb3 - coded input signal and a clock regenerator for carrying out the method. The clock regenerator comprises an input stage for the rectification and for the conversion of the symmetrical input signal into a proportional to the input signal asymmetrical processed input signal; a voltage-controlled oscillator (vco) for generating an oscillator signal with a frequency (f); a phase comparator for comparing the falling edge of the processed input signal with the rising flank of the oscillator signal of the vco, and for generating a comparator signal; a loop - filter for providing a control voltage for vco from the filtered comparator signal of the phase comparator, in such a way that the frequency of the oscillator in the correct phase on the frequency of the input signal is established; and a control stage, which the phase comparator is always then deactivated when a pulse gap of the input signal is present.