Semiconductor memory (DRAM) device capable of reducing its power supply voltage, has for each word line a line decoder having n-channel transistor connected between gate of p-channel transistor and another n-channel transistor

摘要

The semiconductor memory device is designed so that the read-amplifier is limited in order to incorporate a MOS-transistor with a reduced threshold voltage (Vthn) so as to prevent the MOS-transistor becoming less resistant to punch-through, even when the level of channel doping is lowered. The memory arrangement (35) has several discrete cells arranged in several lines and several columns. Each word line has a line decoder, the latter having one n-channel MOS transistor connected between the gate of a p-channel MOS transistor and the gate of another n-channel MOS transistor.