Clock synchronous semiconductor memory has amplitude increase circuit that produces pair of complementary internal read data signals with amplitude level same as external power supply voltage

摘要

The memory location data, in the form of complementary data signals, is received by an amplitude increase circuit (11) in order to produce a pair of complementary internal read data signals with an amplitude level same as the external power supply voltage. An internal power supply circuit (7) produces an internal power supply voltage from an external power supply voltage. An internal circuit (1,3) receives the internal power supply voltage from the internal power supply circuit as an operating voltage in order to select an addressed memory location in a memory location arrangement (2) and to read memory location data from a selected memory location. The memory location data, read by the internal circuit arrangement, is received by an amplitude increase circuit (11) in the form of complementary data signals in order to produce a pair of complementary internal read data signals with an amplitude level same as the external power supply voltage. A transmission circuit (12) receives an operating voltage of amplitude level not lower than the internal power supply voltage to transfer synchronously with an output clock signal (CLK2) the internal read data signals from the amplitude increase circuit. An initial data buffer memory circuit (13) receives an operating voltage of amplitude level not lower than the internal power supply voltage, in order to buffer the data from the transmission circuit. An output buffer (14) receives an output power supply voltage (VDDQ) supplied independently of the external power supply voltage as an operating voltage in order to buffer the buffer memory data of the initial data buffer memory circuit and to output the external read data at an output node (Q).