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Delay control circuit for synchronous dynamic direct access memory has delay model for delaying external clock signal according to asymmetry, control signal generator, two delay devices
Delay control circuit for synchronous dynamic direct access memory has delay model for delaying external clock signal according to asymmetry, control signal generator, two delay devices
The circuit has a delay model for delaying an external clock signal by the asymmetry, a signal generator for producing control signals in response to the clock signals, a delay device with a large delay unit element for delaying the external clock to produce a first delay control loop clock and a second delay device with a small delay unit element for delaying the first delay control loop clock to produce a second delay control loop clock. The circuit has a delay model for delaying an external clock signal (CLK) by the asymmetry (tdl), a signal generator for producing control signals in response to the external and delayed clock signals, a first delay device with a large delay unit element for delaying the external clock signal in response to the control signals to produce a first delay control loop clock signal and a second delay device with a small delay unit element for delaying the first delay control loop clock signal to produce a second delay control loop clock signal.
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