procedures for implementation of read and schreibbefehlen in a multi-level distributed computer system

摘要

A two port high level cache memory for use in a multi-level distributed data processing system includes: 1) a first tag-memory which receives READ commands through one port from a system bus; and 2) a second tag-memory which receives READ commands through another port from a processor bus. The two tag memories store identical sets of comparable addresses. With two tag memories the high level cache memory is able to respond immediately to two different READ commands which occur concurrently on the processor bus and the system bus. Also, a multi-level distributed data processing system includes: 1) a system bus (13) having a main memory (11) coupled thereto; 2) multiple high level cache memories (14), each of which has a first port coupled to the system bus (13) and a second port coupled to a respective processor bus (15); and, 3) each processor bus (15) is coupled to multiple digital computers (17) through respective low level cache memories (16). Further, each low level cache memory (16) stores data words with respective tag bits which identify each data word as being shared (S), modified (M) or invalid (I) but never exclusive; and, each high level cache memory (14) stores data words with respective tag bits which identify each data word as being shared (S), modified (M), invalid (I), or exclusive (E). By identifying a data word in a low level cache memory (16) as shared (S), even when that data word is not in any other low level cache memory, the high level cache memories (14) are able to prevent two computers (17) on separate processor busses (15) from modifying that data word differently.