Biasing of island-surrounding material to suppress reduction of breakdown voltage due to field plate acting on buried layer/island junction between high and low impurity concentration regions

摘要

The reduction in breakdown voltage of a device which contains adjoining regions of relatively high and low impurity concentrations within a dielectrically isolated island of an integrated circuit architecture is effectively countered by biasing the material surrounding the island, such as a support polysilicon substrate or the fill material of a isolated trench, at a prescribed bias voltage that is insufficient to cause the avalanche-generation of electron-hole pairs in the vicinity of the relatively high-to-low impurity concentration junction between the buried layer and the island. Where a plurality of islands are supported in and surrounded by a common substrate material of an overall integrated circuit architecture, the prescribed bias voltage may be set at a value that is no more positive than half the difference between the most positive and the most negative of the bias voltages that are applied to the integrated circuit. Where respective islands do not share a common (continuously connected) substrate, the surrounding material of each island is biased at a voltage sufficiently close to the island voltage as to prevent avalanche-generation of carrier pairs; this voltage may be the same bias voltage applied to the island material itself.