A low jitter fractional divider with low circuit speed constraint comprising a divider 11 for dividing the frequency of an input first clock signal ck by an integer number, c, to obtain a second clock signal ck' and a fractional divider 12 for dividing the second clock signal ck' by a fraction number, b/a, to obtain an output voltage signal ov, a compensation circuit 13 for receiving the output voltage signal ov and generating an output clock signal cka with low jitter. The circuit 13 comprises an adjust buffer 131 for generating an adjust signal based on the output voltage signal ov and a feedback of the output clock signal cka, wherein the buffer 131 has a value which is decreased when the output voltage signal ov asserts a pulse until reaching a predetermined minimum and is increased when the output clock signal cka asserts a pulse until reaching a predetermined maximum, and a down-counter 132 which performs a counting operation for generating the output clock signal cka wherein the down-counter 132 is loaded with a count value determined by a, b and c based on the adjust signal and the feedback of the output clock signal cka when a zero value is reached in said down-counter, thereby adjusting the output clock signal to reduce jitter.
展开▼
