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Test system and methodology to improve stacked NAND gate based critical path performance and reliability
Test system and methodology to improve stacked NAND gate based critical path performance and reliability
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机译:测试系统和方法,以改善基于堆叠的与非门的关键路径性能和可靠性
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摘要
A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.
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