Macroblock variance estimator for MPEG-2 video encoder

摘要

A hardware accelerator for a coding system for pictures includes an array of lines and columns of pixels, and calculates the variance of macroblocks of a digitized video image for a real-time coding of the current image together with the preceding and successive images, according to the MPEG-2 video algorithm. The architecture minimizes the silicon area needed for implementing the hardware accelerator for a cost-effective reduction on the CPU of the coding system. The use of a plurality of distinct filter/demultiplexers of known architectures is eliminated by conveying the incoming pixels to the respective input lines of distinct variance calculation paths by the use of a simple counter.