Speeding up levelized compiled code simulation using netlist transformations

摘要

Delay-independent cycle-based logic simulation of synchronous digital circuits with levelized compiled code simulation has substantially increased speed. Sweep, eliminate, and factor reduce the number of literals. The use of cofactoring, a register allocation and spill scheme, an inverter minimization scheme, and retiming further reduce the simulation time for two and four valued simulation. A shift minimization scheme reduces time in four-valued simulation. The faster simulation is embodied in a method, a computer system, and a computer program product.