首页> 外国专利> Method for filling a dual damascene opening having high aspect ratio to minimize electromigration failure

Method for filling a dual damascene opening having high aspect ratio to minimize electromigration failure

机译:填充具有高长宽比的双镶嵌开口以最小化电迁移失败的方法

摘要

A method for effectively filling a dual damascene opening having a via hole and a trench that are contiguous openings uses a two step deposition process. The method includes a step of filling the via hole by electroless deposition of a first conductive material into the via hole. A second conductive material is at a bottom wall of the via hole, and the second conductive material at the bottom wall of the via hole acts as an autocatalytic surface during the electroless deposition of the first conductive material within the via hole. The method also includes the step of depositing a seed layer of a third conductive material to cover walls of the trench and includes the step of filling the trench by electroplating deposition of the third conductive material from the seed layer into the trench. The present invention may be used to particular advantage for small geometry integrated circuits when the conductive material filling the via hole and the trench is copper. By first filling the via hole using electroless deposition, void formation and poor via contact is prevented. In addition, the more widely available and easily manufacturable electroplating deposition process is still used for filling the trench.
机译:有效地填充具有作为连续开口的通孔和沟槽的双金属镶嵌开口的方法使用两步沉积工艺。该方法包括通过将第一导电材料化学沉积到通孔中来填充通孔的步骤。第二导电材料在通孔的底壁处,并且在第一导电材料在通孔内的无电沉积期间,在通孔的底壁处的第二导电材料充当自催化表面。该方法还包括沉积第三导电材料的种子层以覆盖沟槽的壁的步骤,并且包括通过将第三导电材料从种子层电镀沉积到沟槽中来填充沟槽的步骤。当填充通孔和沟槽的导电材料是铜时,本发明可以特别有利地用于小几何形状的集成电路。通过首先使用化学沉积来填充通孔,可以防止形成空隙和不良的通孔接触。另外,仍然使用更广泛可用且易于制造的电镀沉积工艺来填充沟槽。

著录项

  • 公开/公告号US6245670B1

    专利类型

  • 公开/公告日2001-06-12

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US19990253480

  • 发明设计人 SERGEY LOPATIN;ROBIN CHEUNG;

    申请日1999-02-19

  • 分类号H01L214/763;

  • 国家 US

  • 入库时间 2022-08-22 01:04:07

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