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Digital frequency phase locked loop (FPLL) for vestigial sideband (VSB) modulation transmission system

机译:用于残留边带(VSB)调制传输系统的数字频率锁相环(FPLL)

摘要

In a digital frequency phase locked loop (FPLL) for a grand alliance (GA) HDTV receiver using a vestigial sideband (VSB) modulation transmission system, the digital FPLL for a VSB transmission system having a VCO and a plurality of NTSC carrier eliminating filters for eliminating interference of NTSC adjacent channels includes a filter for eliminating high-frequency components by converting a digital signal output from one of the plurality of NTSC carrier eliminating filters, a delay for delaying the high-frequency-component-eliminated signal by a predetermined width so that its frequency-versus-phase characteristics are changed linearly, symbol inverter for inverting the symbol of the digital signal output from another of the plurality of NTSC-carrier eliminating filters, a switch for selectively outputting the symbol-inverted signal and the digital signal output from another filter, a second filter for limiting the selectively output signal to a predetermined frequency band, a digital-to-analog (D/A) converter for converting the band-limited-digital signal into an analog signal. The result is that the frequency-versus-phase characteristics of the filter is linear, and the size of digital ASICs gates are remarkably reduced.
机译:在使用残余边带(VSB)调制传输系统的大联盟(GA)HDTV接收机的数字频率锁相环(FPLL)中,用于VSB传输系统的数字FPLL具有VCO和多个NTSC载波消除滤波器,用于消除NTSC相邻信道的干扰的滤波器包括:通过转换从多个NTSC载波消除滤波器之一输出的数字信号来消除高频分量的滤波器;用于将消除高频分量的信号延迟预定宽度的延迟器,其频率与相位特性线性变化的符号反相器,用于将从多个NTSC载波消除滤波器中的另一个NTSC载波消除滤波器输出的数字信号的符号反相,用于选择性地输出符号反相信号的开关和数字信号输出来自另一个滤波器的第二滤波器,用于将选择性输出的信号限制到预定频带,即数字模数转换器(D / A),用于将带宽受限的数字信号转换为模拟信号。结果是,滤波器的频率与相位特性是线性的,并且数字ASIC门的尺寸显着减小。

著录项

  • 公开/公告号US6249559B1

    专利类型

  • 公开/公告日2001-06-19

    原文格式PDF

  • 申请/专利权人 L.G. ELECTRONICS INC.;

    申请/专利号US19960702094

  • 发明设计人 JUNG-SIG JUN;

    申请日1996-08-23

  • 分类号H03D32/40;H03D30/00;H04L272/20;H04N54/55;

  • 国家 US

  • 入库时间 2022-08-22 01:04:00

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