首页>
外国专利>
Snooping a variable number of cache addresses in a multiple processor system by a single snoop request
Snooping a variable number of cache addresses in a multiple processor system by a single snoop request
展开▼
机译:通过单个侦听请求侦听多处理器系统中可变数量的缓存地址
展开▼
页面导航
摘要
著录项
相似文献
摘要
Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.
展开▼