Priority-based shared bus request signal mediating circuit

摘要

A bus request signal mediating circuit comprises an input section for latching a plurality of bus request signals occurring within a certain period of time and for suppressing a new input of bus request signals occurring outside the certain period before the processing for all of the input bus request signals is completed. A plurality of bus request signals which are input within the certain period of time are processed consecutively based on the priority among the bus request signals stored in the register.