首页> 外国专利> Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system

Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system

机译:在多处理计算机系统中的内存读取操作过程中保持高速缓存一致性并节省系统内存带宽的消息传递方案

摘要

In a multiprocessing computer system, a cache-coherent data transfer scheme that also conserves the system memory bandwidth during a memory read operation is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and sending respective probe responses to the source node. Probe command also causes the node having an updated copy of the cache block to send the cache block to the source node through a read response. The target node, concurrently with the probe command, initiates a read response transmission to send the requested data to the source node. The node having the modified cached copy containing the requested data transmits a memory cancel response to the target node concurrently with the updated copy of the cache block to the source node. The memory cancel response attempts to prevent the target node from sending to the source node the stale data from the system memory. The memory cancel response also causes the target node to send a target done response to the source node. The source node waits for probe responses, read responses and the target done message prior to sending a source done message to the target node.
机译:在多处理计算机系统中,描述了在存储器读取操作期间也节省系统存储器带宽的高速缓存一致性数据传输方案。源处理节点向目标处理节点发送读取命令,以从与目标处理节点关联的系统存储器中的指定存储位置读取数据。响应于读取的命令,目标处理节点将探测命令发送到计算机系统中的所有其余处理节点,而不管其余节点中的一个或多个是否具有在其各自的高速缓冲存储器中高速缓存的数据的副本。探测命令通过适当地更改包含请求数据的缓存块的状态并将相应的探测响应发送到源节点,来使每个节点保持缓存一致性。探测命令还使具有高速缓存块的更新副本的节点通过读取响应将高速缓存块发送到源节点。目标节点与probe命令同时启动读取响应传输,以将请求的数据发送到源节点。具有包含所请求数据的修改后的缓存副本的节点将缓存取消响应与缓存块的更新副本同时发送到目标节点,同时将其发送到源节点。内存取消响应尝试阻止目标节点将系统内存中的过时数据发送到源节点。内存取消响应还使目标节点向源节点发送目标完成响应。在将源完成消息发送到目标节点之前,源节点等待探测响应,读取响应和目标完成消息。

著录项

  • 公开/公告号US6275905B1

    专利类型

  • 公开/公告日2001-08-14

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US19980217649

  • 发明设计人 JAMES B. KELLER;DERRICK R. MEYER;

    申请日1998-12-21

  • 分类号G06F120/00;

  • 国家 US

  • 入库时间 2022-08-22 01:03:33

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