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Optimization of integrated circuit properties through constraints using a dominant time constant
Optimization of integrated circuit properties through constraints using a dominant time constant
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机译:通过使用主导时间常数的约束来优化集成电路的性能
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摘要
A method for optimizing an integrated circuit uses a dominant time constant of a transition of the circuit. A physical layout of the circuit is characterized in terms of design parameters. The circuit is modeled by a conductance matrix G and a capacitance matrix C, wherein G and C are affine functions of the design parameters. The optimization method comprises the step of finding the values of the design parameters that optimize a property of the circuit while simultaneously enforcing a constraint that the dominant time constant must be less than a maximum value tmax. Mathematically, the constraint on the dominant time constant can be written: tmax GC0. The optimization method can be used when the circuit has a non-tree topology. Furthermore, when the design parameters comprise variables that relate to sizes of elements of the circuit, a topology of the circuit is optimized by the optimization method. In some embodiments the circuit is optimized for a plurality of transitions, and in some embodiments the design parameters are subject to design constraints.
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机译:用于优化集成电路的方法使用电路的过渡的主要时间常数。根据设计参数来表征电路的物理布局。该电路由电导矩阵G和电容矩阵C建模,其中G和C是设计参数的仿射函数。该优化方法包括以下步骤:找到优化电路特性的设计参数的值,同时执行一个约束,即主导时间常数必须小于最大值t max Sub>。在数学上,可以将主导时间常数的约束写为:t max Sub> GC0。当电路具有非树形拓扑时,可以使用优化方法。此外,当设计参数包括与电路的元件的尺寸有关的变量时,通过优化方法来优化电路的拓扑。在一些实施例中,电路针对多个过渡进行了优化,并且在一些实施例中,设计参数受到设计约束。
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