PURPOSE: To reduce the length and processing time of adder by adjusting the cell at each level so that the number of input signals to the adder circuit at the next level can be reduced. ;CONSTITUTION: The basic multiplier cell of a multiplier which calculates the multiplication of, for example, eight bits is adjusted. When the calculated results obtained by adjusting the adder at the first level are added to the adder at the next level, the basic multiplier cell at the bit position 9 of the adder at the second level can utilize only three inputs. Consequently, no output appears at the terminal of the second level step 9 of the adder, because the same adjustment as that usually performed for transferring the input placed at the terminal can be performed. This does not give any influence to an 8-bit multiplier, but affects a 16bit multiplier. Since the cell at each level can be adjusted to reduce the number of input signals to the adder circuit of the next level, the length of adder can be shortened.;COPYRIGHT: (C)1993,JPO
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