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BAND LIMIT CIRCUIT, COMMUNICATION DEVICE, COMMUNICATION NETWORK SYSTEM, AND BAND LIMITING METHOD

机译:带限电路,通信设备,通信网络系统和带限方法

摘要

PROBLEM TO BE SOLVED: To provide a band limit circuit and band limiting method, capable of limiting a band at a PHY layer level in a communication network system as well as a communication device and communication network system capable of limiting a band for every communication line, by solving the problem of a band being difficult to be limited for each communication line which is provided to a user, because it is not possible to determine whether a plurality of packets have been transmitted on the same communication line.;SOLUTION: A cycle counter 3 counts the number of clocks CLKA generated by frequency-dividing a transmission clock CLK. A comparator circuit 7 outputs a clear signal B1, when the count value exceeds the holding value of a cycle register 5. A limit counter 4 counts the number of clock CLKB of AND of an effective frame signal A1 and the clock CLKA. An over limit detecting circuit 8 outputs a limit exceedance detecting signal B3, when the count value B2 exceeds the holding value of a limit register 6. An effective frame signal control circuit 9 controls, when the over limit detecting signal B3 is inputted, so that the effective frame signal A1 is invalidated and outputs an effective frame signal A3.;COPYRIGHT: (C)2002,JPO
机译:解决的问题:提供一种频带限制电路和频带限制方法,其能够在通信网络系统中在PHY层级限制频带,以及能够对每条通信线路限制频带的通信装置和通信网络系统通过解决难以为提供给用户的每个通信线路限制频带的问题,因为不可能确定是否在同一通信线路上已经发送了多个分组。计数器3对通过对发送时钟CLK进行分频而生成的时钟CLKA的数量进行计数。当计数值超过周期寄存器5的保持值时,比较器电路7输出清除信号B1。极限计数器4对有效帧信号A1与时钟CLKA的AND的时钟CLKB的数量进行计数。当计数值B2超过极限寄存器6的保持值时,极限检测电路8输出极限超过检测信号B3。当输入了极限检测信号B3时,有效帧信号控制电路9进行控制。有效帧信号A1无效并输出有效帧信号A3 。;版权:(C)2002,JPO

著录项

  • 公开/公告号JP2002135287A

    专利类型

  • 公开/公告日2002-05-10

    原文格式PDF

  • 申请/专利权人 FUJIKURA LTD;

    申请/专利号JP20000325891

  • 发明设计人 KATAYAMA HIDEO;YAMADA YASUTO;

    申请日2000-10-25

  • 分类号H04L12/46;H04L12/28;H04L7/00;H04L7/02;H04L12/44;

  • 国家 JP

  • 入库时间 2022-08-22 00:53:48

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