首页> 外国专利> Clock-generating circuit and image-forming apparatus having a function of canceling F-theta property errors

Clock-generating circuit and image-forming apparatus having a function of canceling F-theta property errors

机译:具有消除F-θ特性误差的功能的时钟发生电路和图像形成装置

摘要

The invention concerns a clock-generating circuit, which generates dot clock pulses for driving a light-emitting element employed in an optical-writing section of an image-forming apparatus and has a function of canceling f&thgr; property errors caused by a f&thgr; lens employed in the image-forming apparatus. The clock-generating circuit includes a digital-delay dot clock adjusting section to adjust timings of rising-edges or falling-edges of the dot clock pulses generated by changing a selection for a plurality of delayed-clock pulses, which are generated by delaying clock-pulses, outputted from a reference oscillator, in slightly different delay times; and a controlling section to control a selecting operation for the plurality of delayed clock pulses, performed in the digital-delay dot clock adjusting section, so as to compensate for f&thgr; property errors caused by the f&thgr; lens employed in the optical-writing section.
机译:本发明涉及一种时钟发生电路,其产生点时钟脉冲以驱动用于图像形成装置的光学写入部中的发光元件,并且具有消除f&thr的功能。 f&thgr引起的财产错误;成像设备中使用的镜头。时钟产生电路包括数字延迟点时钟调节部分,以调节通过改变多个延迟时钟脉冲的选择而产生的点时钟脉冲的上升沿或下降沿的定时,所述多个延迟时钟脉冲是通过延迟时钟而产生的。 -从参考振荡器输出的脉冲,其延迟时间略有不同;控制部分控制在数字延迟点时钟调节部分中执行的对多个延迟时钟脉冲的选择操作,以补偿f&thgr。 f&thgr;引起的财产错误;光学写入部分中使用的镜头。

著录项

  • 公开/公告号US2002135668A1

    专利类型

  • 公开/公告日2002-09-26

    原文格式PDF

  • 申请/专利权人 KONICA CORPORATION;

    申请/专利号US20020093753

  • 发明设计人 KOUICHI TAKAKI;SHINJI MORITA;

    申请日2002-03-08

  • 分类号B41J2/385;B41J2/435;B41J2/40;B41J2/405;G03G13/04;

  • 国家 US

  • 入库时间 2022-08-22 00:52:44

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