Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect

摘要

A method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation is disclosed. The method comprises providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired using in sensing operation of a memory cell in the memory array. The first embodiment is presented by assigning a first pair of the bit lines permuted with each other to create a non-neighboring bit line layout. The second embodiment is presented by inserting one of a second pair of the bit lines into a first pair of bit lines to separate the first pair of bit lines in layout design. The method further comprises shrinking the layout space between two adjacent non-paired bit lines. Thereby, the method contributes to the reduction of metal bit line coupling effect without any trade off of integrated circuit density by modifying the circuit layout of metal bit lines to a non-neighboring bit line arrangement in a memory array.