MODIFIED PHASE INTERPOLATOR AND METHOD TO USE SAME IN HIGH-SPEED,LOW POWER APPLICATIONS

摘要

A phase interpolator which includes cross-coupled switches and is configured to receive a plurality of input clock phases and generate a new output clock phase based on the input clock phases which are selected by the cross-coupled switches. The cross-coupled switches are controlled by selection inputs. The phase interpolator may be configured to receive four clock phases, but preferably is configured to receive eight clock phases. Preferably, the phase interpolator includes eight cross-coupled switches, such as two sets of four cross-coupled switches. Preferably, each set of switches is controlled by a different selection input. Hence, a first selection input controls one set of four cross-coupled switches, and a second selection input controls the other set of four cross-coupled switches. Preferably, each pair of switcheswherein each pair includes a switch from each setis configured to receive the same clock phase. Specifically, each pair may be configured to receive a given, pre-determined clock phase (if the phase interpolator is configured to receive four clock phases), or a selector device such as a multiplexer can be connected to each pair of switches such that a clock phase can be selected from a plurality of clock phases (such as where the phase interpolator is configured to receive eight clock phases). The phase interpolator may be configured for analog or digital control.