Level 2 cache architecture for multiprocessor with task_ID and resource_ID

摘要

A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity with corresponding tag arrays (502(n)), four segments per entry and four valid and dirty bits. Each tag entry (1236) includes task-ID qualifier field (522) and a resource ID qualifier field (520). Accesses to the cache are qualified by comparing (1244) a task ID and resource ID proffered with a cache request to values stored in the tag entry.