A method and apparatus for single cycle, cache line invalidation within a cache memory is described. The method includes enabling memory cells within a cache state array of the cache memory. An invalid state is then written to each memory cell within the cache state array of the cache memory. The enabling of the memory cells within the cache state array of the cache memory occurs during a first phase of a clock cycle. While the writing of the invalid state to each memory cell within the cache state array of the cache memory occurs during a second phase of the clock cycle. Consequently, cache line invalidation of each cache line within the cache memory occurs within a single clock cycle formed by the first phase of the clock cycle and the second phase of the clock cycle. In partial invalidation of the cache memory is possible by way-subdividing the cache state array or set-subdividing the cache state array. One shot or single cycle cache line invalidation reduces the total time required for invalidation of all cache lines within the cache memory to just a clock cycle. The implementation is simple with minimal changes to the cache array limited only to those cells that store the state information of the cache lines. Since many system operations necessitate invalidation of the entire cache, one-shot invalidation clearly improves the system performance with no significant impact on the die size.
展开▼
