Clock signal analysis device and clock signal analysis method

摘要

A clock signal analysis device (100, 200, 300) has a pre-processing section (4) for reading circuit connection information, transistor characteristic information, and control information stored in memories (1, 2, 3) and for editing those information to be used for a simulation by a simulation execution section (5). The simulation execution section (5) executes a simulation of circuit operation, and then an after-processing section (6) calculates a delay value from a clock signal input node to a clock signal terminal node, a difference between delay values of clock signal terminal nodes, a rising time, a falling time of the clock signal and displays an analysis result by using a two-dimensional distribution map through a monitor (8).