Method of automatically generating schematic and waveform diagrams for analysis of timing margins and signal skews of relevant logic cells using input signal predictors and transition times

摘要

Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells. Timing margin (set up and hold time) and signal skew (change in signal timing) are derived under best and worst case functional conditions by determining differences in the transition times of the predictive input waveforms for the cells of the logic cone.