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Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation
Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation
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机译:用于在程序控制下同时或按可选子集顺序测试一组多个芯片的电子系统,以限制芯片功耗
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摘要
A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal.
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