Construction and application for non-volatile, reprogrammable switches

摘要

The present invention includes a DRAM technology compatible non-volatile, reprogrammable switch formed according to an DRAM optimized process flow. The non-volatile, reprogrammable switch includes a non-volatile memory cell. The non-volatile memory cell includes a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. A capacitor is formed in a subsequent layer above the first MOSFET and is separated from the MOSFET by an insulator layer. A vertical electrical via couples a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET. A second MOSFET is formed in the semiconductor substrate. The gate of the first MOSFET also serves as a gate of the second MOSFET. Additional MOSFETs can be combined in a similar fashion with the non-volatile cell to create a new, powerful logic cell that is smaller and more robust than conventional circuit solutions. The present invention includes applications such as a very size efficient address decode tree, data routing device, or other applications such as used in DRAM redundancy schemes. Methods for forming and using the present invention are also included. The need for intervening sense amps normally required to read the status of a non-volatile memory cell (e.g. an EEPROM cell) and communicate this to additional logic that would then in turn control the status of one or more switches is eliminated. Thus, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.