Pre-amplifier design for high-speed analog-to-digital converters

摘要

The present invention overcomes the gate leakage drawback existing in advanced CMOS technologies to achieve extremely high-speed analog-to-digital conversion. The circuit and method employ an input offset storage (IOS) technique to calibrate the differential comparator device during an auto-zero cycle. The reference voltage and offset voltages are stored on capacitors coupled to the inputs of the differential comparator device during the auto-zero cycle. A source follower is placed between each capacitor and the inputs to the differential comparator device. The source followers are selected to prevent leakage from the capacitors during a conversion mode. Additionally, switches utilized in feedback loops for auto-zeroing the differential comparator are also selected to prevent leakage of the capacitors in the conversion mode.