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Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof
Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof
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机译:能够容易地测试选通信号和数据信号的时序标准的半导体存储装置及其附属装置和测试装置
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摘要
A first delay circuit for delaying a data signal IND output from a memory circuit and a second delay circuit for delaying a strobe signal INS, and a latch circuit for latching data according to the outputs of the first and the second delay circuits are provided as a test circuit inside a DDR SDRAM. A tester can observe results of latching by the latch circuit to facilitate determination whether the data signal and the strobe signal have a correlation adapted to a standard. Accordingly, such a DDR SDRAM can be provided that is capable of conducting an examination whether the device meets a tDQSQ standard defining a correlation between the strobe signal DQS and the data signal DQ with ease.
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