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Scratchpad RAM memory accessible in parallel to a primary cache
Scratchpad RAM memory accessible in parallel to a primary cache
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机译:Scratchpad RAM内存可并行访问主缓存
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摘要
A low-latency scratchpad RAM memory system is disclosed. The scratchpad RAM memory system can be accessed in parallel to a primary cache. Parallel access to the scratchpad RAM memory can be designed to be independent of a corresponding cache tag RAM, thereby enabling the scratchpad RAM memory to be sized to any specification, independent of the size of the primary cache data RAMs.
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