Content addressable memory cell and design methodology utilizing grounding circuitry
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机译:利用接地电路的内容可寻址存储单元和设计方法
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摘要
A CAM cell design methodology and a method of pre-charge and comparison timing is disclosed. A CAM cell utilizing this design methodology includes grounding circuitry and a P-channel transistor configured to communicate a comparison result to a match line using the Miller effect. In one embodiment, the CAM cell further includes a positive comparison bit line, a negative comparison bit line, a first dual-ended CAM memory core cell configured to store data, a second dual-ended CAM memory core cell configured to store masking data, comparison circuitry, and a second P-channel transistor configured to communicate a masked state to the match line.
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