YI Pulse Width Control circuit

摘要

PURPOSE: A column control signal pulse width control circuit is provided to prevent a fail data in a "READ" or a "WRITE" operation by using signal pulse width for controlling a column control signal pulse width through delay parts having a respectively different delay time. CONSTITUTION: A column control signal pulse width control circuit comprises a logic compositional part(ND11) receiving an enable signal(CASATV) and a source voltage(VDD), a latch part(10) latching it by an output signal(D1) of the logic compositional part(ND11) and a delay signal, a first and a second delay parts(20,30) controlling a delay rate by controlling time constant using an output signal(D2) of the latch part(10) and an inverted signal(D4) of the signal(D2), a first and a second transfer parts(TG1,TG2) selectively supplying an output signal(D5) or the other output signal(D6) of the delay parts(20,30) as a delay signal by a write enable signal(WE), buffering parts(INV14,INV15) supplying a control signal for controlling a pulse width of a column control signal by buffering the output signal(D2) of the latch part(10), and a switching part(NM11) selectively resetting the control signal for controlling the pulse width of the column control signal.