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Flexible Memory Address Mapping Circuit for CPU Max Processing

机译:灵活的内存地址映射电路,用于CPU最大处理

摘要

PURPOSE: A flexible memory address mapping circuit for CPU max processing is provided to make the CPU carry out the high performance process by configuring a main memory with DRAM(SRAM)+SRAM and to improve the entire processing gain of the CPU by floatingly changing a position according to a software request of the SRAM. CONSTITUTION: The circuit for mapping the memory address comprises the CPU(13) controlling the entire system and outputting an address signal and a control signal for decoding, an address decoder(40) converting the address and control signal output from the CPU into the decoding and control signal, and a PLD(Programmable Logic Device)(15) consisting of a module(20) capable of changing the memory position of the SRAM(19). The memories(18a,18b,19) receive the memory control signal output from the PLD and a buffer(17) transfers the address and the data by positioning between the CPU and the memories.
机译:用途:提供了用于CPU最大处理的灵活的内存地址映射电路,以通过将主存储器配置为DRAM(SRAM)+ SRAM来使CPU进行高性能处理,并通过浮动更改内存来提高CPU的整体处理增益。位置根据SRAM的软件要求。构成:用于映射存储器地址的电路包括:CPU(13)控制整个系统并输出地址信号和用于解码的控制信号;地址解码器(40)将从CPU输出的地址和控制信号转换为解码控制信号; PLD(可编程逻辑器件)(15),其由能够改变SRAM(19)的存储位置的模块(20)组成。存储器(18a,18b,19)接收从PLD输出的存储器控​​制信号,并且缓冲器(17)通过定位在CPU和存储器之间来传送地址和数据。

著录项

  • 公开/公告号KR20020045305A

    专利类型

  • 公开/公告日2002-06-19

    原文格式PDF

  • 申请/专利权人 LG ELECTRONICS INC.;

    申请/专利号KR20000074716

  • 发明设计人 YOO DEUK HYEONG;

    申请日2000-12-08

  • 分类号G06F12/06;

  • 国家 KR

  • 入库时间 2022-08-22 00:30:53

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