A method and apparatus for implementing TURBO decoder

摘要

PURPOSE: A turbo code decoding apparatus structured with a hardware structure of a turbo decoder is provided to perform an interactive decoding with an element decoder a pair of log likelihood ratio(LLR) memories and a first-in first-out(FIFO) structure. CONSTITUTION: A turbo code decoding apparatus for decoding a turbo encoded signal at high speed for use in a communication system includes an alpha metric calculation circuit, an alpha metric memory, a branch metric memory, a beta metric generating circuits, an LLR generating circuit to form an element decoder(210) as Max-Log-MAP decoder structured in such a way that a decoded output comes out inversely with respect to an order of input. The turbo code decoding apparatus further includes a last-in first-out(LIFO) structure memory for changing the inverted order to a corrected order, The turbo code decoder performs a high speed decoding of a low consumption power with a minimum size by being constructed with the element decoder(210), the two LLR memory(220,230), the FIFO structure memory(200), an adder(270), a subtractor(260) and a controller(190).