Data input/output line scheme to reduce resistance of data input/output line

摘要

The data input-output line structure to reduce the resistance of the data input and output lines are provided. The present invention relates to a semiconductor memory device, the memory cell data is input and output via the data input-output line, a data input-output line has a first signal line on a first signal line of the first metal layer, which is connected to the bit lines of the memory cell and the first signal lines and the second signal line of the second metal layer, which is wired in the same direction, having a first signal line and the plurality of strapping connection connecting the second signal line and the second metal layer has a smaller resistance value than the first metal layer, the first to the second signal line is wired perpendicularly to the bit line direction of the memory cell.