Memory architecture with multilevel hierarchy

摘要

The present invention relates to a memory architecture consisting of memory cells with a multi-level hierarchy having a plurality of external connection ports. That kind of memory is also commonly referred to as multi-port memory. A presented multi-port-memory architecture with multi-level hierarchies typically has 1-port-memory cells at the lowest hierarchical level. The higher hierarchical level memory blocks consist of lower hierarchical level memory blocks. Surface cost on a chip can be reduced through the proposed multi-port-memory architecture with a multi-level hierarchy. At this time, the memory blocks of the hierarchical level are arranged in a switching-network manner, banking-technology-array, and the like according to the conditions in the memory block matrix. Therefore, the maximum possible design freedom is provided by use. Multi-port-memory architectures also have circuitry for handling access conflicts. The provided memory architecture can be applied to all memory technologies and logic technologies.