Intermediate digital memory element for transmitting flank signals from an interrupt generator to a CPU without any dead time being caused by the transfer

摘要

Digital intermediate memory component (1) for transfer of a received display signal flank from a first digital circuit, where the signal flank indicates a condition change in the first digital circuit, to a second digital circuit. Both digital circuits are asynchronously connected t each other. The intermediate memory component is reset after successful transfer of the signal flank and is then ready to transmit a second signal flank. The first digital circuit is an interrupt signal generator, while the second circuit is a CPU data processing unit.