In-situ structurization and cleaning of metal wiring of semiconductor, used for producing device, integrated circuit or connection between them, uses 3-stage reactive ionic etching and fourth etching stage to remove polymer

摘要

In-situ structurization and cleaning of metal wiring of semiconductor with dielectric; barrier (B1), metal (M) and barrier (B2) layers and resist pattern comprises 4-stage reactive ionic etching, in one chamber, through (1) B2 to form polymer (P1) over its side walls; (2) M to expose B1 and form polymer (P2) over P1 and its side walls; and (3) B1 to form polymer (P3) over P1 and P2; and (4) to remove all polymers, using gases containing (1, 2, 3) (a) boron and chlorine (Cl), (b) Cl, (4) (c) Cl, (d) fluorocarbon. Process for in-situ structurization and cleaning of metal wiring for semiconductor equipment involves providing a semiconductor structure with overlying dielectric layer; first barrier layer (B1), metal layer (M), second barrier layer (B2) and resist pattern and etching in 4 consecutive stages in the same chamber. The etching stages comprise (1) reactive ionic etching through (B2) to form a first polymer layer (P1) over the side walls of (B2); (2) etching (M) to expose (B1) and form a second polymer (P2) over (P1) and the side walls of (M); (3) etching (B1) to form a third polymer layer (P3) over (P1) and (P2); and (4) removing (P1), (P2) and (P3). Stages (1, 2, 3) are carried out with a gas containing boron (B) and chlorine (Cl) and a gas containing Cl and stage (4) with a gas containing Cl and a gas containing fluorocarbon. Independent claims are also included for 2 methods (A, B) for producing a pattern and in-situ cleaning of metal wiring for a semiconductor device.