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Semiconductor memory device has word configuration selection stage that selects word configuration for normal mode from number of configurations if deactivated test mode signal input
Semiconductor memory device has word configuration selection stage that selects word configuration for normal mode from number of configurations if deactivated test mode signal input
The device has a test mode recognition circuit that deactivates a test mode signal in normal mode and activates in response to an externally supplied test mode determination signal. A word configuration selection stage (8) selects a word configuration for use in normal mode from a number of configurations if the deactivated test mode signal is input. Data are entered and output on the basis of the selected word configuration.
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