Data reception circuit for serial input data stream separates data stream into data streams with reduced transmission rate for parallel processing before reconstruction via clocked logic circuit

摘要

The data reception circuit has a data stream separation stage (4), providing several data streams with a reduced data transmission rate, a reference clock generator (13) providing a clock frequency corresponding to the reduced transmission rate, fed to a delay circuit (12) with a delay element chain and asynchronous and synchronous clocked register fields (8,17), inserted between the separation stage and a synchronous clocked logic circuit (18) for reconstruction of the serial input data stream.