A universal asynchronous data bus, for linking different device types together, has a twin wire connection with a data line and an enable line, once a header packet is received enable is set to one until transmission ends

摘要

Serial bus system for data transfer in which once a data packet head with 16 bit length receiver, sender, internal address and data has been received on a data line an enable line is set to one. The enable line is set to one independent data can be transmitted. The bus system has only two lines a data and an enable line and no clock line is necessary.