For high-speed swellable deal with of a plurality of interruptions

摘要

PURPOSE: To provide a processor capable of multiple interruption and attaining a fast responsiveness to an interruption process without being limited by registers which can be used for the interruption process. ;CONSTITUTION: The processor consists of dedicated registers 6-8 which hold specific information relating to the execution of a program, a general register 3 which holds unspecific information relating to the execution of the information, a 1st register 4 which holds information indicating banks currently in use, a 2nd register 5 which holds information showing a return bank, and a bank memory 2 equipped with plural banks for which the pieces of information held in the 2nd register 5, dedicated registers 6-8, and general register 3 are transferred not through an external bus.;COPYRIGHT: (C)1993,JPO&Japio