首页> 外国专利> DRUM GEAR WITHOUT CAPACITY OF SILIZIUM-AUF ISOLATOR SUBSTRATE

DRUM GEAR WITHOUT CAPACITY OF SILIZIUM-AUF ISOLATOR SUBSTRATE

机译:无硅-AUF隔离剂基质的滚筒齿轮

摘要

A DRAM device has a first semiconductor region of one conductivity on the silicon film of a silicon-on-insulator substrate. A second and a third semiconductor region of the opposite conductivity type are formed in the first semiconductor region. A fourth semiconductor region of the same conductivity type as the first semiconductor region is formed within the second semiconductor region with higher doping concentration. An insulating layer is formed on the semiconductor surface. On top of the insulating layer, a gate electrode is formed and is at least partially overlapped with the first, the second, the third, and the fourth semiconductor region. A storage node is formed in the first semiconductor region between the second and the third semiconductor region where the information is stored. The amount of charge stored in the storage node is controlled by a first transistor including the fourth semiconductor region, the second semiconductor region, the storage node, and the gate electrode. The charge stored in the storage node will affect the characteristics of a second transistor including the third semiconductor region, the storage node, the second semiconductor region, and the gate electrode, thereby the information stored in the storage node is detected.
机译:DRAM器件在绝缘体上硅衬底的硅膜上具有一个导电率的第一半导体区域。在第一半导体区域中形成导电类型相反的第二和第三半导体区域。在第二半导体区域内以较高的掺杂浓度形成与第一半导体区域相同的导电类型的第四半导体区域。在半导体表面上形成绝缘层。在绝缘层的顶部上,形成栅电极并且该栅电极与第一,第二,第三和第四半导体区域至少部分地重叠。在存储信息的第二和第三半导体区域之间的第一半导体区域中形成存储节点。存储节点中存储的电荷量由包括第四半导体区域,第二半导体区域,存储节点和栅电极的第一晶体管控制。存储在存储节点中的电荷将影响包括第三半导体区域,存储节点,第二半导体区域和栅电极的第二晶体管的特性,从而检测存储在存储节点中的信息。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号