MICRO CONTROL UNIT WITH CONDITIONAL AVOIDANCE OF THE UPDATE OF THE HOLDING CIRCUIT FOR THE HIGH-QUALITY BITS AND WITH DIRECT CONTROL OF THE LOW-QUALITY BITS OF STORAGE ADDRESSES

摘要

A microcontroller which directly drives a memory with low order address bits during a fetch operation. Driving the low order address bits directly while the high order bits are latched during an address/data multiplex on the same pins allows the latch enable cycle to be skipped during sequential fetches. A sequential address detector indicates when the latch enable cycle can be skipped.