High security data encryption and decryption controller for electronic monetary transfers has CPU, ROM, RAM input/output interface and encryption/decryption and clear text writing section on a single semiconductor chip without a data bus

摘要

The controller has (10A), a CPU (11A) for program execution; a ROM (13A) for program storage; a RAM (12A) used as work zone when the CPU executes the program; data input/output (14A), and; a section for decryption of encrypted data and writing the data in clear text form; the whole of the above is formed on a single semiconductor (100A). The RAM (12A) memorizes a private key used to decrypt encrypted data. The controller (10A) has a waiting mode for data being received from an external device (100) and an authorization mode controlling an operation. It has means for switching modes for decryption of data from the external device in waiting mode, with the memorized private key in ROM, so that the clear text data is reestablished. The switching means also verifies if the clear text data coincides with the memorized data in ROM and switches the encryption control onto authorization mode as a function of coincidence or of difference in the data. The ROM (13A) memorizes a number of principal programs executed in authorization mode. The encryption controller has a principal program selector to select one of the programs to be executed in the authorization mode on the basis of data emitted by the external device in waiting mode.