首页> 外国专利> Digital network test circuit includes microprocessor analyzing both logical state and detailed analogue voltage levels for analysis of errors

Digital network test circuit includes microprocessor analyzing both logical state and detailed analogue voltage levels for analysis of errors

机译:数字网络测试电路包括微处理器,可同时分析逻辑状态和详细的模拟电压电平以分析错误

摘要

The tester comprises a line interface circuit (1) which determines, on its output (4), the logical state. An analogue-digital converter (5) digitizes the electrical voltage values on the data lines and stores them. A microprocessor (11) then analyses the time series of stored data. The tester comprises a line interface circuit (1) which determines, on its output (4), the logical state corresponding to the signals presented on the data lines (H,L) of a network to be tested. An analogue-digital converter (5) digitizes at high speed the electrical voltage values presented on the data lines and sends them for storage in a memory (10) at the same time as the logical states presented on the output (1). A microprocessor (11) then analyses the time series of stored data. The tester is thus able to carry out a combined analysis on the logical state and the physical state of the network, to monitor accurately the rise times of the electrical voltage level, the fall times and the dominant electrical levels.
机译:该测试器包括线路接口电路(1),该线路接口电路在其输出(4)上确定逻辑状态。模数转换器(5)将数据线上的电压值数字化并存储。然后,微处理器(11)分析所存储数据的时间序列。该测试器包括线路接口电路(1),该线路接口电路(1)在其输出(4)上确定对应于在要测试的网络的数据线(H,L)上呈现的信号的逻辑状态。模数转换器(5)高速数字化显示在数据线上的电压值,并将其与输出(1)上显示的逻辑状态同时发送,以存储在存储器(10)中。然后,微处理器(11)分析所存储数据的时间序列。因此,测试仪能够对网络的逻辑状态和物理状态进行组合分析,以准确监控电压电平的上升时间,下降时间和主要电平。

著录项

  • 公开/公告号FR2815125A1

    专利类型

  • 公开/公告日2002-04-12

    原文格式PDF

  • 申请/专利权人 NSI;

    申请/专利号FR20000013252

  • 发明设计人 BERENGER JEAN YVES;

    申请日2000-10-11

  • 分类号G01R31/08;

  • 国家 FR

  • 入库时间 2022-08-22 00:24:19

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