The automatic generation method in the entry string for simulation based logical verification and output manner and device null of the state cutting time series in order to generate the device and the entry string for that logical verification

摘要

PROBLEM TO BE SOLVED: To shorten the period of logic verification and to improve the reliability. ;SOLUTION: Respective parts in a state transition specification procedure execution part 101 executes respective instructions in a state transition specification procedure. Namely, a state set specification part 107 interprets and executes an instruction specifying a set of states. An image calculation part 108 interprets and executes an instruction specifying the calculation of an image of the set of states. A set arithmetic part 109 interprets and executes an instruction specifying set operation between sets of states. A set comparison part 110 interprets and executes an instruction specifying comparing operation between the sets of states. A time and state set registration part 111 interprets and executes an instruction which registers the sets of states and the times corresponding to the sets of states as a state set time series. A procedure type general instruction execution part 112 interprets and executes procedure type general instructions including integer arithmetic instructions and control instructions. Then an input time series generation part 102 generates an input string for logic verification for actualizing part or the whole of the state set time series.;COPYRIGHT: (C)1997,JPO