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PHASE NOISE REDUCTION CIRCUIT, PHASE MODULATOR, PHASE DEMODULATOR AND HIGH-FREQUENCY COMMUNICATION SYSTEM

机译:相位噪声降低电路,相位调制器,相位解调器和高频通信系统

摘要

PROBLEM TO BE SOLVED: To provide a phase noise reduction circuit, a phase modulator and a phase demodulator which effectively reduce phase noise from an oscillator with a simple configuration, allow a multi-stage connection without disturbing the operation of the phase noise reduction circuit such as PLL circuits, and to provide a high-frequency communication system which reduces phase noise mixing in from a local oscillator and improves communication quality.;SOLUTION: A semiconductor limiter circuit 5 limits the power level of an input signal. A power level phase adjusting circuit 6a adjusts the power level and the phase of a signal which passes through the limiter circuit 5 and a power level phase adjusting circuit 6b adjusts the power level and the phase of the input signal. A power combiner 4 combines the signals having the power levels and the phases adjusted by the adjusting circuits 6a, 6b and outputs a signal, thus canceling phase noise components to extract only the sinusoidal signal components.;COPYRIGHT: (C)2003,JPO
机译:要解决的问题:为了提供一种相位噪声降低电路,相位调制器和相位解调器,以简单的配置有效地降低来自振荡器的相位噪声,允许多级连接而不会干扰相位噪声降低电路的操作,例如作为一个锁相环电路,并提供一种高频通信系统,它可以减少来自本地振荡器的相位噪声混入并提高通信质量。解决方案:半导体限制器电路5限制输入信号的功率电平。功率电平相位调整电路6a调整通过限制器电路5的信号的功率电平和相位,并且功率电平相位调整电路6b调整输入信号的功率电平和相位。功率组合器4组合具有由调节电路6a,6b调节的功率电平和相位的信号并输出​​信号,从而消除相位噪声分量以仅提取正弦信号分量。;版权:(C)2003,JPO

著录项

  • 公开/公告号JP2003218712A

    专利类型

  • 公开/公告日2003-07-31

    原文格式PDF

  • 申请/专利权人 SHARP CORP;

    申请/专利号JP20020008790

  • 发明设计人 AMANO YOSHIHISA;

    申请日2002-01-17

  • 分类号H04B1/10;

  • 国家 JP

  • 入库时间 2022-08-22 00:15:00

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